The integrated circuit (IC) manufacturing technology have been moving forward as the metal-oxide-semiconductor field-effect transistors (MOSFET's) become smaller and smaller to improve the performances such as increased switching speed, lowered power consumption and higher level of integration. HKMG (high-k metal gate) technology promises to enable scaling of the transistors as well as reduced stand-by power due to a reduction in gate leakage.
In the HKMG technology, aluminum is often used as a conductor of the metal gate. The metal gate resistance (Rs_MG) increases with the thinning of aluminum of the metal gate, which causes the device characteristics to change with the processing parameters of aluminum of the metal gate. For example, for I/O devices with a larger gate area than that of the core devices, dishing due to over-polishing often happens in low pattern density areas (for example, the gate area of an I/O device), during the chemical-mechanical polishing (CMP) planarization process. As a result, the metal gate resistance (Rs_MG) increases with the thinning of aluminum of the metal gate to enhance the threshold voltage (V) and lower the turn-on current (Ion). Even worse, threshold voltage mismatch occurs for paired I/O devices due to thickness difference between the metal gates when dishing appears. Both of the above lead to chip malfunction.
To overcome the problems due to dishing of the metal gate by the CMP process, there is need in providing a semiconductor device and a method for manufacturing the same to prevent chip malfunction.